Workshop on Computer Architecture Education

Held in conjunction with the

31st International Symposium on Computer Architecture

Munich, Germany
Saturday, June 19, 2004

Final Program

Session 1. Welcome and Invited Talk 8:00-8:55

  8:00  Welcome, Edward F. Gehringer, workshop organizer

  8:10   Invited talk, "The changing role of computer architecture education within CS curricula," Reiner Hartenstein, Technical University of Kaiserslautern (Paper)

Session 2. Field Programmable Gate Arrays 9:00-10:00

  9:00   "A computer architecture education curriculum through the design and implementation of original processors using FPGAs," Yutaka Sugawara and Kei Hiraki, University of Tokyo (Paper)

  9:15   "Teaching embedded systems with FPGAs throughout a computer science course," Vanderlei Bonato, Ricardo Menotti, Eduardo Simões and Eduardo Marques, Universidade de São Paulo; Marcio M. Fernandes, Universidade Metodista de Piracicaba (Brazil) (Paper)

  9:30   "Extending FPGA-based teaching boards into the area of distributed memory multiprocessors," Michael Manzke and Ross Brennan, Trinity College, Dublin (Ireland) (Paper)

 9:45  Discussion

Break 10:00-10:30

Session 3. HDLs and Other Topics 0:30-12:00

 10:30   "Teaching computer architecture using an architecture description language," Sandro Rigo, Marcio Juliato, Rodolfo Azevedo, Guido Araújo, and Paulo Centoducatte, U. of Campinas (Brazil) (Paper)

 10:50   "RTeasy: An algorithmic design environment on register-transfer level," Hagen Schendel, Carsten Albrecht, and Erik Mähle, University of Lübeck (Paper)

 11:05   "Creating sharable learning objects from existing digital course content," Rajendra G.Singh, Margaret Bernard, and Ross Gardler, University of the West Indies (Trinidad) (Paper)

 11:25   "Introduction to formal processor verification at logic level: A case study," Paul Amblard, Fabienne Lagnier, and Michel Levy, Université Joseph Fourier (France) (Paper)

 11:45  Discussion

Lunch 12:00-1:00

Session 4. Keynote 1:00-1:55

  1:00   Keynote, "The case for breadth in computer architecture education," Bill Dally, Stanford University (USA) (Paper)

Session 5. Visualization 2:00-2:45

  2:00   "Visualising the MMIX superscalar pipeline—not only for teaching purposes," Axel Böttcher, Munich U. of Applied Sciences (Paper)

  2:15   "Bridges to computer architecture education," Peter Marwedel, Birgit Sirocic, University of Dortmund (Paper)

 2:35  Discussion

Poster Session 2:45-3:45

  2:45   Introduction of posters, All poster presenters

  3:00  Posters and break

          "Improving Instruction Set Architecture Learning Results," José M. Claver, María I. Castillo, and Rafael Mayo, Univ. Jaume I (Spain) (Paper)

          "Integrating research and e-learning in advanced computer architecture courses," Mouna Nakkar, U. of Sharjah (United Arab Emirates) (Paper)

          "Bridging undergraduate learning and research in software and hardware," Liang Cheng and Dale Parson, Lehigh University (USA) (Paper)

          "Teaching basics of instruction pipelining with HDLDLX," Miloš Becvár, Czech Technical University in Prague (Czech Republic) (Paper)

          "Software implementations of division and square-root operations for Intel Itanium processors," Marius Cornea, Intel Corporation (USA) (Paper)

          "Visual simulator for ILP dynamic OOO processor," Anastas Misev, Marjan Gusev, St. Cyril & Methodius U. (Republic of Macedonia) (Paper)

          "WebMIPS: A new Web-based MIPS simulation environment for computer architecture education," Irina Branovic, Roberto Giorgi, and Enrico Martinelli, University of Siena (Italy) (Paper)

          "DARC2: Second-generation DLX architecture simulator," Roger Luis Uy, Marizel Bernardo, and Josiel Erica, De La Salle U. (Philippines) (Paper)

          "MKit simulator for introduction of computer architecture," Seikoh Nishita, Takushoku U. (Japan) (Paper)

Session 6. Simulation Environments 3:45-5:00

  3:45  "Pin: A Binary Instrumentation Tool for Computer Architecture Research and Education," Vijay Janapa Reddi, Alex Settle, and Daniel A. Connors, University of Colorado; Robert S. Cohn, Intel Corporation (USA) (Paper)

  4:05   "A simulation applet for microcoding exercises," Roland Ibbett, University of Edinburgh (UK) (Paper)

  4:20   "SimCore/Alpha functional simulator," Kenji Kise, Takahiro Katagiri, Hiroki Honda, and Toshitsugu Yuba, U. of Electro-Communications (Japan) (Paper)

  4:35   "A combined virtual and remotely accessible microprocessor laboratory," Helmut Bähring Jörg Keller, and Wolfram Schiffmann, FernUniversität Hagen (Paper)

 4:45  Discussion

Session 7. Open Forum on Textbook Pricing 5:00-

Led by Denise Penrose, Morgan Kauffman/Elsevier